1. Technical Field:
The present invention relates generally to the field of computer architecture and, more specifically, to methods and systems for managing resources among multiple operating system images within a logically partitioned data processing system.
2. Description of Related Art:
A logical partitioning option (LPAR) within a data processing system (platform) allows multiple copies of a single operating system (OS) or multiple heterogeneous operating systems to be simultaneously run on a single data processing system platform. A partition, within which an operating system image runs, is assigned a non-overlapping sub-set of the platform""s resources. These platform allocable resources include one or more architecturally distinct processors with their interrupt management area, regions of system memory, and I/O adapter bus slots. The partition""s resources are represented by its own open firmware device tree to the OS image.
Each distinct OS or image of an OS running within the platform are protected from each other such that software errors on one logical partition cannot affect the correct operation of any of the other partitions. This is provided by allocating a disjoint set of platform resources to be directly managed by each OS image and by providing mechanisms for ensuring that the various images cannot control any resources that have not been allocated to it. Furthermore, software errors in the control of an OS""s allocated resources are prevented from affecting the resources of any other image. Thus, each image of the OS (or each different OS) directly controls a distinct set of allocable resources within the platform.
One means for separating the partitions is managed by a firmware component, such as, for example, the hypervisor within an RS/6000 platform, a product of International Business Machines Corporation of Armonk, N.Y. Hardware errors that are fatal to this firmware component become fatal for the entire platform, thus, bringing down the entire system. One major hardware error that may affect the hypervisor is an instruction fetch unrecoverable memory error (IfetchUE). The Risc system 6000 memory, within the RS/6000, is single bit error correction code protected, that is, hardware is able to correct any single bit error by special redundancy codes. However, currently, multi-bit errors cannot be corrected, but may only be detected. Multi-bit errors, while rare, occur due to a variety of conditions. Therefore, a method, system, and apparatus for recovering and isolating errors affecting the hypervisor is desirable.
The present invention provides a method, system, and apparatus for recovering from an instruction fetch error. In one embodiment, a data processing system maintains a primary copy and an alternate copy of a set of instructions for a software component. The instructions for performing the processes of the software component are fetched from the primary copy for execution by a processor. A pair of pointers is maintained in each copy identifying the beginning of each copy. Responsive to a determination that an instruction fetch error has been received, a corresponding current instruction in the alternate copy is determined and the software component is restarted by fetching and executing instructions from the alternate copy starting with the corresponding current instruction. The corresponding current instruction is determined by subtracting the beginning address of the copy with the error from the address of the current instruction, then adding the beginning address of the alternate copy.